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MPIB63S-68KX3 (PC-133 256MB 168pin Registered SDRAM DIMM)
DESCRIPTION
The MPIB63S-68KX3 is 32M bit x 72 Synchronous Dynamic RAM high density memory module. The MPIB63S-68KX3 consists of eighteen CMOS 16M x 8 bit with 4 banks Synchronous DRAMs in TinyBGA package, three 18-bits Drive ICs for input control signal, one PLL in 24-pin TSSOP package for clock and one 2K EEPROM in 8-pin TSSOP package for Serial Presence Detect on a 168-pin glassepoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The MPIB63S-68KX3 is a Dual in-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system application.
FEATURES
* Performance range - 133Mhz Max. Freq. (CL=3) * Burst mode operation * Auto & self-refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V0.3V power supply * MRS cycle with address key programs * Latency (Access from column address) * Burst Length (1, 2, 4, 8 & Full page) * Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB: Height (1200 mil), double sided component
1
PIN CONFIGURATIONS (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD /WE DQM0 DQM1 /CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CLK0 Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front VSS DU /CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP **SDA **SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD /CAS DQM4 DQM5 /CS1 /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 *A12 Pin 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back VSS CKE0 /CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD
PIN NAME
Pin Name A0~A12 BA0~BA1 DQ0~DQ63 CB0 ~ 7 CLK0~CLK3 CKE0~CKE1 /CS0~/CS3 /RAS /CAS /WE DQM0~7 VDD VSS REGE SDA SCL SA0 ~ 2 WP DU NC Function Address input (Multiplexed) Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable DQM Power supply (3.3V) Ground Register enable Serial data I/O Serial clock Address in EEPROM Write protection Don't use No connection
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD
PIN CONFIGURATION DESCRIPTION
Pin CLK /CS CKE System clock Chip select Clock enable Name Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling al inputs except CLK, CKE and DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1 CLK+t SS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address: RA0 ~RA11, Column address: CA0 ~CA9 Selects bank too be activated during row address latch time. Select bank for read/write during column address latch time. Latches row address on the positive going edge of the CLK with /RAS low. Enable row access & precharge. Latches column address on the positive going edge of the CLK with /CAS low. Enable column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active.(Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the address and control inputs are latched if CLK is held at a high or low logic level. Th e inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to V DD through 10K ohm Register on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data input/output are multiplexed on the same pins. Check bits for ECC. WP pin is connected to VSS through 47K ohm Resistor. When WP is "high", EEPROM Programming will be inhibited and the entire memory will be write-protected. Power and ground for the input buffers and the core logic.
A0 ~ A11
Address
BA0 ~ BA1 /RAS /CAS /WE DQM0 ~ 7 REGE
Bank select address Row address strobe Column address strobe Write enable Data input/output mask Register enable
DQ0 ~ 63 CB0 ~ 7 WP
Data input/output Check bit Write protection
VDD/VSS
Power supply/ground
2
May 2001
Rev:1.0
BCS1 PCLK0 BCS0 B0CKE0 B0A0~B0A11,B0BA0~1,B0RAS,B0CAS,B0WE BDQM0 DQ0~7 10
* *
*
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D0
*
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D9
*
DQ32~39 10 PCLK1
*
D1
*
D10
* *
* * * * *
*
D2
*
D11
*
BDQM1 DQ8~15 10 PCLK2
*
D3 * *
D12
BDQM2 DQ40~47 10 B2CKE0
BDQM3 CB0~7 10 PCLK3 BCS2 B1CKE0 BDQM4 DQ16~23 10 PCLK4 B3CKE0
CLK CS CKE Add,CTL DQM DQ0~7
D4
CLK CS CKE Add,CTL DQM DQ0~7
D13
*
* *
CLK CS CKE Add,CTL DQM DQ0~7
D5
*
* D6 * *
CLK CS CKE Add,CTL DQM DQ0~7
D14
* *
*
BDQM5 DQ48~55 10 BCS3
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D15
* D7 * * * D8
*
*
D16
BDQM6 DQ24~31 10 PCLK5
*
D17
B1A0~B1A11,B1BA0~1,B1RAS,B1CAS,B1WE BDQM7 DQ56~63 10
VSS VDD 2G AGND 1G AVCL
B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0
A3~A10,BA0
SN74ALVC162835
V DD
10k
PCLK6 REGE A11,BA1 CS2,CS3 CKE0 DQM2,3,6,7
CDC2509 LE OE
B0A11,B0BA1 B1A11,B1BA1 BCS2, BCS3 B0CKE0,B1CKE0 B2CKE0,B3CKE0 BDQM2,3,6,7
10 CLK0 12pF CLK FIBIN
Cb*2
IY0 IY1 IY2 IY3 IY4 2Y0 2Y1 2Y2 2Y3
PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5
FBOUT
SN74ALVC162835
LE
A0~A2 RAS,CAS,WE DQM0,1,4,5 CS0,CS1
OE
B0A0~B0A2 B1A0~B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BDQM0,1,4,5 BCS0, BCS1
* Note 1. Unused clock termination : 10 and 12pF 2. The actual values of Cb will depend upon the PLL chosen.
SN74ALVC162835
Serial PD SCL WP 47K A0 A1 A2 SDA
LE
OE
SA0 SA1 SA2
3
May 2001
Rev:1.0
ABSOLUTE MAXIMUM RATIINGS
Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD , VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +125 18 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RANTINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC OPERATING CONDITIONS AND CHARACTERISTIICS
Recommended operating conditions(Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Symbol Min Typ Max Unit Note Supply Voltage VDD , VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD +0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 V IOH = -2mA Output logic low voltage VOL 0.4 V IOL = 2mA Input leakage current ILI -10 10 uA 3
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 5ns 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 5ns 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200mV)
Pin Address (A0 ~ A11, BA0 ~ BA1) /RAS, /CAS, /WE CKE (CKE0 ~ CKE1) Clock (CLK0 ~ CLK1) /CS (/CS0 ~ /CS1) DQM (DQM0 ~ DQM7) DQ (DQ0 ~ DQ63) REGE Symbol CADD CIN CCKE CCLK CCS CDQM COUT CREGE Min Max 8 8 8 6 8 8 8 5 Unit pF pF pF pF pF pF pF pF
4
May 2001
Rev:1.0
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) (Note: 1, 2, 3, 4) Parameter/Condition Symbol Max Unit Note IDD1 OPERATING CURRENT: Active Mode; 1,800 mA 5, 6, Burst = 2; READ or WEITE; tRC = tRC (MIN); 7, 8 CAS latency = 3 STANDBY CURRENT: Power-Down Mode; IDD2 36 mA 8 CKE = LOW; All banks idle IDD3 STANDBY CURRENT: Active Mode; S0#, S1# = HIGH; 900 mA 5, 7, CKE = HIGH; All banks active after tRCD met; 8, 9 No access in progress IDD4 OPERATING CURRENT: Burst Mode; Continuous burst; 1,800 mA 5, 6, READ or WRITE; All banks active; 7, 8 CAS latency = 3 AUTO REFRESH CURRENT: tRC= tRC(MIN); IDD5 3,240 mA 5, 6, 7, 8, CKE = HIGH; S0# = HIGH; CL = 3 IDD6 54 mA 10, 12 tRC = 15.325s; CL = 3 IDD7 36 mA 11 SELF REFRESH CURRENT: CKE 0.2V
Note: 1. All voltage referenced to VSS. 2. An initial pause of 100s is required after power-down, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously, VSS and VSSQ must be at the same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the t REF refresh requirement is exceeded. 3. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to the 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 4. I DD specifications are tested after the device is properly initialized. 5. I DD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. The I DD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 7. Address transitions average one transition every two clocks. 8. t CK = 7.5ns. 9. Other input signals are allowed to transition no more than once every two clocks and ate otherwise at valid VIH or VIL levels. 10. CKE is HIGH refresh command period (t RFC [Min]) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 11. Enables on-chip refresh and address counters. 12. Other input signals ate allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels.
5
May 2001
Rev:1.0
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.1 tr/tf = 1/1 1.4 See Fig. 2 Unit V V Ns V
3.3V
Vtt = 1.4V
1.2K Ohm
50 Ohm
Output
870 Ohm
50 pF
VOH(DC) = 2.4V IOH = -2mA VOL(DC) = 0.4V IOL = 2mA
Output ZO=50 Ohm
50 pF
(Fig.1) DC output load circuit
(Fig.2) AC output load circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter Row active to row active delay /RAS to /CAS delay Row precharge time Row active time Symbol tRRD (min) tRCD (min) tRP (min) tRAS(min) tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to Active delay tDAL (min) Last data in to new col. Address delay tCDL(min) Last data in to burst stop tBDL(min) Col. Address to col. Address delay tCCD (min) Number of valid output data CAS latency = 3 CAS latency = 2
Then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and teas burst stop. 5. t RDL = 1 CLK and t DAL = 1 CLK + 20 ns is also support. Kingmax recommends t RDL = 2 CLK and t DAL = 2 CLK + 20 ns.
Version 15 20 20 44 120 66 2 2 CLK + 20ns 1 1 1 2 1
Unit ns ns ns ns us ns CLK CLK CLK CLK ea
Note 1 1 1 1 1 2, 5 5 2 2 3 4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
6
May 2001
Rev:1.0
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE
Parameter CLK cycle time CAS latency=3 CAS latency=2 CLK to valid output delay CAS latency=3 CAS latency=2 Output data hold time CAS latency=3 CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Note: 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2 -1]ns should be added to the parameter.
Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ
100MHz Min Max 7.5 1000 10 5.4 6 2.7 3 2.5 2.5 1.5 0.8 0.8 5.4 6
Unit ns ns ns ns ns ns ns ns ns
Note 1 1, 2 2 3 3 3 3 2
7
May 2001
Rev:1.0
BURST DEFINITION
Burst Starting Order of access within a burst length Col. addr. Type=Sequential Type=Interleaved
A0 0 0-1 1 1-0 4 A1 A0 00 0-1-2-3 01 1-2-3-0 10 2-3-0-1 11 3-0-1-2 8 A2 A1 A0 000 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 010 2-3-4-5-6-7-0-1 011 3-4-5-6-7-0-1-2 100 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 110 6-7-0-1-2-3-4-5 111 7-0-1-2-3-4-5-6 Full n=A0-A9 Cn , Cn+1 , Cn+2 , Cn+3 , Page (location Cn+4 .......C,Cn n-1 (1,024) 0-1,023) 2 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported
Note: 1. For a burst length of two, A1-A9 select the block of two Burst ; A0 selects the starting column within the block. 2. For a burst length of four, A2-A9 select the block of four burst; A0-A1 select the starting column within the block. 3. For a burst length of eight, A3-A9 select the block of four burst; A0-A2 select the starting column within the block. 4. For a full page burst, the full row is selected and A0A9 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A0-A9 select the unique column to be accessed and Mode Register bit M3 is ignored.
8
May 2001
Rev:1.0
SIMPLIFIED TRUTH TABLE
Command Register Refresh Mode register set Auto refresh Self Entry refresh Exit CKEn- CKEn /CS /RAS
1
/CAS L L H X H L
/WE L H H X H H
DQM BA0,1 X X X X X V V
A10 /AP OP code X X
A11 , A9 ~A0
Note 1, 2 3 3 3 3
H H L H H
X H L H X X
L L L H L L
L L H X L H
Bank active & row address Read & Auto precharge Col. addr. disable Auto precharge enable Write & Auto precharge Col. addr. disable Auto precharge enable Burst stop P recharge Bank selection All banks Clock suspend or Entry active power down Exit Precharge power Entry down mode Exit DQM No operation command
H
X
L
H
L
L
X
V
H H H L H L H H
X X L H L H
L L H L X H L H L
H L X V X X H X V X H X L H
H H X V X X H X V X H
L L X V X X H X V X H
X X X X X X V X
V X
Row address L Col. 4 Addr. (A0 ~A9 ) 4, 5 H L Col. 4 Addr. (A0 ~A9 ) 4, 5 H X 6 L X H X
X
X
X X
7
(V = Valid, X = Don't care, H = Logic high, L = logic low) Note: 1. OP Code: Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatic precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" a t read, write, row active and precharge, bank D is selected. If A10 /AP is "High" at row precharge, BA 0 and BA1 is ignored and all banks ate selected. 5. During burst read or write with auto prechatge, new read/write command can not be issued. Another bank read/write command can issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. burst stop command is valid at every burst length. 7. DQM sampled at positive go ing edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
9
May 2001
Rev:1.0
10
May 2001
Rev:1.0

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